1. Field of the Invention
This invention relates to scan testing, and more particularly, to the bypassing of secure registers coupled to scan elements.
2. Description of the Related Art
Circuitry to support scan testing may provide internal access to an integrated circuit (IC). Scan circuitry may be implemented by forming chains of scannable elements. Data may be serially shifted through the scannable elements of the scan chain. This may allow for the input of test stimulus data, as well as the capture and shifting out of test result data. Using available scan circuitry, manufacturing tests may be conducted on ICs prior to their shipment to a customer in order to verify the circuitry therein. Scan circuitry may also support hardware debugging during the development phase of an IC, providing information for future revisions thereof.
Since scan chains may provide internal access to an IC, they may have use that extends beyond manufacturing test. One of these uses is support for the debugging of software that is being designed to operate on the IC. Software in a development phase may require extensive debugging in order to remove errors and arrive at a finished product. Some of the errors in the software may be related to the manner in which it interacts with the circuitry of a chip. Accordingly, when an error is encountered during the debugging of software executing on the IC, scan circuitry may be used to capture internal data that can be used to analyze the problem. In some cases, scan circuitry may support a scan dump, which may enable the capture of an internal state of the chip. Scan circuitry may also support a memory dump, which can enable the capture of contents of one or more memories (e.g., register files, random storage memories, caches, etc.) in the IC. Accordingly, scan dumps and memory dumps may provide a useful tool for analysis of software bugs that occur during the development process.